Conventional current-steering techniques have been widely used for high-speed sigma-delta Digital-to-Analog converters (ΣΔ DAC) for deep sub-micron technologies. To meet linearity requirements, unit current cells should be well matched, which requires a large silicon area. Accordingly, transistor matching is becoming more difficult and “area expensive” as processes scale smaller (<22 nm). Alternatively, dynamic element matching or self-current calibration techniques have been conventionally used to compensate for mismatches between unit current DAC cells. These alternative techniques, however, also occupy extra silicon area, while limiting the maximum DAC operation speed. Accordingly, conventional current-steering architectures presently used for DACs are not area-efficient.
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